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High Speed Logic Memory Tester Disclosure Number: IPCOM000056069D
Original Publication Date: 1980-Oct-01
Included in the Prior Art Database: 2005-Feb-13

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Buettner, HM Hart, LL Kane, PH [+details]


The functional test system of the figure includes a tester 5, a fixture 6 for interfacing to a known good device and a device under test, and a high speed test system processor 7. The tester 5 simultaneously applies input signals from input buffer 9 and bus 10 to a known good card on lines 12 and a device under test on lines 14. A hardware compare circuit 16 compares the output signals from the pins of the device under test received on bus 18 on a real-time basis with the corresponding output signals from the pins of the known good device on bus 20. The output of window buffer 22 degates data comparison for any pin during valid transition times for the particular pin. The window buffer 22 can also be used to capture output information from a device for characterization.