Detection of Erroneous Inputs in Finite-State Machines
Original Publication Date: 1980-Oct-01
Included in the Prior Art Database: 2005-Feb-13
Telecommunication protocols and other interfaces are often specified in terms of finite-state machines (FSMs) in order to ensure that every possible condition is defined unambiguously. An FSM sequences among its various states in a manner completely defined by the current state of the FSM and (at least) one current input to the FSM. It is frequently desirable to identify certain inputs as erroneous when the FSM is in particular states.