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High Speed Error Correcting Encoder Decoder

IP.com Disclosure Number: IPCOM000056107D
Original Publication Date: 1980-Oct-01
Included in the Prior Art Database: 2005-Feb-13

Publishing Venue

IBM

Related People

Authors:
Mears, JC [+details]

Abstract

The use of dual read-only memories (ROMs) for table look-up in an error correcting encoder/decoder enables high speed asynchronous operation and simplified control logic. Encoder/decoder operation is described here with respect to the (24, 12) Golay code; however, the dual ROM configuration may be readily applied to other error correcting codes e.g. the Hamming code.