Browse Prior Art Database

Merged And/Or Array PLA Using Double Polysilicon FET Process

IP.com Disclosure Number: IPCOM000056136D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Greenspan, SB Kraft, WR Moore, VS Rhodes, JC Stahl, WL Thoma, NG [+details]

Abstract

A bit path through a standard program logic array can be modeled with AND and NOR gates. In field-effect transistor (FET) technologies, such an array is realized using NOR arrays which are personalized to realize the desired logic function. The input to the AND array may be either true, complemented or multiple bit partitioned. This type of structure leads to near optimum densities in metal gate technologies because the layout can be done without any contact holes in the array.