Multi Input Low Skew Buffer Driver
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14
The figure shows a multi-input, low skew clock driver circuit. The output of depletion-mode transistor 1 drives the gates of depletion-mode transistor 3 and enhancement-mode transistors 6 and 8. If data is low, transistor 1 becomes high, causing the gates of transistors 3, 6 and 8 to be high. This turns on transistor 8, causing the OUT line to go low. At the same time, transistor 3 drives the OUT line to a high level.