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Multi Function Synchronizing Register Disclosure Number: IPCOM000056142D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

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Related People

Brown, LW Downs, ES Hanover, HC Payne, GW [+details]


This arrangement provides for multiple usage of a register for establishing data lock-in, calculating a cyclic redundancy check (CRC) character and detecting CRC failures during data read operations. A significant logic saving is obtained by using the CRC register as a data synchronous lock-in zero-detect mechanism. Adding the proper control lines allows the register to perform direct shifting and detect 16 or 32 adjacent zero bits in the main data stream. This is a critical step in establishing synchronism with the media.