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Interfacing Different Microprocessor Systems

IP.com Disclosure Number: IPCOM000056143D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Massman, LH Wildes, DV [+details]

Abstract

Using the circuit 8 shown in Fig. 1, components from significantly different specialized architectures can be combined into a unique, high-performance circuit that heretofore was not available to designers. Circuit 8 connects together a microprocessor 10 of one architecture and peripheral support chips 12 for a microprocessor of a different architecture, such as the universal synchronous/asynchronous receiver/transmitter (USART), e.g., the Intel 8251A. Using a combined software/hardware approach, the architecturally imposed timing and data bus structure incompatibilities can be resolved without significantly affecting the throughput of microprocessor 10 and without requiring an inordinate amount of unit logic in circuit 8.