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This process provides a dense self-aligned AND logic or read-only memory array in double polysilicon processing technology.
English (United States)
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Self Aligned, Ion Implanted Read Only Memory
This process provides a dense self-aligned AND logic or read-only memory
array in double polysilicon processing technology.
A semiconductor wafer 10 is initially provided with parasitic device protection,
such as recessed oxide (not shown). Areas of wafer 10 in which active devices
are to be formed are provided with a gate oxide 12 followed by an enhancement
channel tailoring ion implant, if required. Next, a non-critical mask is used to
selectively ion implant depletion device channel regions 11 for devices to be
formed using the first-level polysilicon as their gate electrodes. This implant
should be as shallow as possible in order to enable removal by etching in
subsequent steps, as required. Next, the first-level polysilicon gate electrodes 14
are defined by etching a blanket-deposited polysilicon layer in the presence of
masking or photoresist portions 16 (Fig. 1).
Leaving the photoresist 16 in place, exposed gate oxide 12 is removed by dip
etching followed by a reaction ion etch of the exposed wafer surface to a depth to
remove any misaligned depletion implant species not under gate electrodes 14
and photoresist 16 (Fig. 2).
Next, a second selective depletion implant 18 is provided for device channel
regions associated with second-level polysilicon gate electrodes. This is followed
by an oxidizing step to grow thermal oxide 20 over exposed polysilicon and wafer
surfaces. A second enhancement device channel tailor...