High Noise Immunity Column Select Sense Amplifier Circuit
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14
This circuit significantly reduces the sensitivity between adjacent selected and unselected bit lines of a memory array, particularly of the read-only-store type. This circuit may also be used to sense information stored in a single transistor when two independent digits of information are stored in the same transistor.