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Planar Sputtered SiO/2/ Process Producing Damage Free PtSi

IP.com Disclosure Number: IPCOM000056176D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Proctor, RW Smith, DC [+details]

Abstract

The present process for applying a sputtered layer of silicon dioxide uses a high voltage bias which sometimes results in the erosion of the platinum silicide not covered by metal. This may lead to a nonuniform thickness of silicon dioxide deposited over the platinum silicide. In some cases no silicon dioxide is deposited, resulting in electrical shorting of the second metal to the silicon. Erosion of platinum silicide also results in irregularities in the reflecting interface, causing inaccurate measurements of silicon dioxide thickness determined from the product wafer normal incidence spectrophotometry (NIS) site. Platinum silicide erosion also causes the wafer serial number to be unreadable.