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High Density, Planar Metal Lands

IP.com Disclosure Number: IPCOM000056177D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Miller, RJ [+details]

Abstract

One method for obtaining closely spaced metal lands, shrinking the size of bipolar transistors, comprises applying N+ polysilicon over the transistor, and etching it away from the base and other unwanted regions (Fig. 1). A CVD (chemical vapor deposited) oxide is then deposited over the wafer (Fig. 2). By doing a blanket RIE (reactive ion etch), the oxide is removed everywhere except at the sides of the polysilicon. The N+ polysilicon can then be preferentially etched away, leaving the oxide sidewalls in place (Fig. 3). A blanket metal is sputtered or evaporated on, and a planarization process performed with photoresist and RIE (Fig. 4).