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Method of Reducing Main Storage Requirements for Deductive Fault Simulation in Combinational Circuits

IP.com Disclosure Number: IPCOM000056183D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Goel, P [+details]

Abstract

This method reduces storage requirements for deductive fault simulation in combinational circuits by (1) calculating each gate in the circuit exactly once, and (2) excising from storage the deductive fault lists for blocks whose "go-to's" have been calculated.