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Functional Debug Chip Disclosure Number: IPCOM000056202D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

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Related People

Klein, W Klink, E Najmann, K Rudolph, V [+details]


In the design phase of an integrated memory chip, the various peripheral circuits have to be analyzed. For this purpose, the chips have to be fully functional when tested after the second level metal. Functionality is guaranteed only if the voltage drops on the voltage buses are very low. On the final (regular) chip, functionality is maintained by third level power shunts. To ensure that the chip on the second level metal is functional, the power shunts required are led out of the active chip area, thus replacing the kerf between the chips (monitor chip). This prevents area losses. When the design phase is completed, the second level power shunts can be removed, and the chip becomes a regular chip requiring power shunts on the third level metal.