N-Bit Multiplexer with Test Feature
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14
This circuit allows the multiplexing of data bus signals into a latch element that can operate in either a parallel or serial mode. Two major advantages are obtained through its usage. 1. A multiplexing feature that is accomplished with the addition of a single IGFET device per bus position; 2. A test feature that can be used to detect/isolate faults.