Revised CCD Memory Block Mode Addressing
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14
Charge-coupled device (CCD) memories have several relevant performance characteristics. Presently available devices have very long storage loops on which paged data is stored. Access time, which is the time necessary for the memory to reach the proper address, is essentially zero for CCD memories. On the other hand, latency, the time between access of the proper CCD address and the start of I/O, tends to be rather long due to the necessity of waiting until the CCDs have shifted to their home or start-of-page location. It should be appreciated that the data transfer rate is a result of the memory organization and CCD shift rate.