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Circuit Card Diagnosis at Machine Speed Disclosure Number: IPCOM000056258D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

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Related People

Hart, LL Kane, PH Lampat, RD [+details]


This article describes a procedure which provides failure diagnosis of a level sensitive scan design (LSSD) circuit card. When an error occurs during operation of a device under test (DUT) in a system environment at system speeds, the tester is stopped and rerun to the failing condition using an external oscillator. A clock counter is used to count the clock cycles of the external oscillator. Upon detection of system failure, the oscillator is stopped, the clock count saved, and the shift register latches (SRLs) scanned out and saved. The tester then reruns the system, applying the same number of clock cycles to a known good circuit card. The SRLs from this known good circuit card are scanned out and compared to the SRL data saved from the DUT circuit card.