Browse Prior Art Database

Method of Fabricating MOSFET Integrated Circuits With Low Resistivity interconnection Lines

IP.com Disclosure Number: IPCOM000056315D
Original Publication Date: 1980-Nov-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Rideout, VL [+details]

Abstract

This article describes a method for fabricating MOSFET integrated circuits having low resistivity (silicide) interconnection lines and polysilicon gate electrodes without additional masking steps. The objective is to preserve the safe and reliable polysilicon gate electrode technology while simultaneously incorporating the high conductivity silicide technique yet without adding any additional masking steps. This is achieved by the novel use of the buried contact masking step, coupled to lift-off silicide.