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A merged transistor logic (MTL) or integrated injection logic (I/2/L) memory cell is made with polysilicon-metal coupling to provide reduced cell size and improved cell switching time.
English (United States)
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Bipolar Memory Cell with Polysilicon Metal Cross Coupling
A merged transistor logic (MTL) or integrated injection logic (I/2/L) memory
cell is made with polysilicon-metal coupling to provide reduced cell size and
improved cell switching time.
The circuit diagram of the memory cell is illustrated in Fig. 1 as a four-device
MTL cell having a pair of word lines WL1 and WL2 and a pair of bit lines B0 and
B1. The cell also includes first and second injectors 10 and 12, each in the form
of a PNP transistor, and first and second inverting devices 14 and 16, each in the
form of an NPN transistor, cross-coupled between their bases and collectors.
Fig. 2 illustrates a layout or plan view of the cell of Fig. 1 integrated into a
silicon substrate 18, with Pigs. 3 and 4 being sectional views taken along lines 3-
3 and 4-4, respectively, of Fig. 1. Deep oxide trenches 20, 22 and 24 are formed
from the surface of substrate 18 to a depth below the N+ subcollectors 26 and 28
which form the word lines WL1 and WL2, respectively. PNP transistor 10,
formed as a lateral transistor, is illustrated in Figs. 2 and 3 by the P+ emitter 30,
N epitaxial region 32 as the base and the P+ collector 34. NPN transistor 14,
formed as a vertical transistor, is also illustrated in Figs. 2 and 3 by N+ collector
36, P base 35 along with P+ region 34 and the N epitaxial region 32 also acting
as an emitter in conjunction with subcollector 26 or word line WL1. PNP
transistor 12, also formed as a lateral transistor, is illustrated in Figs. 2 and 4 by
the P+ emitter 40, N epitaxial region 42 as the base and the P+ collector 44.
NPN transistor 16, formed as a vertical transistor, is also illustrated in Figs. 2 and
4 by N+ collector 46, P+ base 48 along with P+ region 44 and the N epitaxial
region 42 also acting as an...