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A fast, dense, low power and low voltage T/2/L logic circuit or gate is provided by using a merged double diffused PNP transistor to limit saturation of an NPN transistor and as an active load.
English (United States)
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High Density T/2/L Logic Circuit
A fast, dense, low power and low voltage T/2/L logic circuit or gate is
provided by using a merged double diffused PNP transistor to limit saturation of
an NPN transistor and as an active load.
In the operation of the circuit, illustrated in Fig. 1, when
all input voltages applied to the input NPN transistor T10 are high,
transistor T10 and PNP transistor T12 are off, with output NPN
transistor T14 being on, causing the voltage at the output to be low.
Since transistor T12 is off when transistor T14 is on, the collector
current of transistor T14 is reduced, as is power dissipation. When
at least one input voltage applied to the input NPN transistor T10 is
low, both transistors T10 and T12 are turned on, causing transistor
T14 to turn off and the voltage at the output to rise rapidly.
A load resistor Rl is connected to the collector of transistor T10 and, if
desired, a small current-sharing resistor (not shown) may be inserted between
the source of supply voltage Vcc and the common point between the base of
transistor T10 and the emitter of transistor T12. Voltage source Vcc may be as
low as 1.0 volt. As can be seen, the PNP transistor T12 limits the saturation of
NPN transistor T10 and acts as the load for output transistor T14.
The cross section of merged transistors T10 and T12 of Fig. 1 is illustrated in
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