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High Density T/2/L Logic Circuit

IP.com Disclosure Number: IPCOM000056389D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Patel, PT [+details]

Abstract

A fast, dense, low power and low voltage T/2/L logic circuit or gate is provided by using a merged double diffused PNP transistor to limit saturation of an NPN transistor and as an active load.