Logic Array Isolation for Testing
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14
The art has addressed the problem of testing an embedded array  and of testing both logic and embedded arrays  where the design conformed with LSSD (Level Sensitive Scan Design) rules . The problems of testing (i) unconstrained logic containing embedded arrays and (ii) static logic containing dynamic embedded arrays have not been addressed earlier and are solved by this article. This article encompasses the technique of (1] to test an embedded array and also provides a mechanism to test the containing logic without accessing the array.