Scanning Electron Microscope Stage for Testing Integrated Circuits
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14
It is known to measure voltage and timing at internal nodes in an integrated circuit (IC) using the electron beam as a probe. In  the Scanning Electron Microscope (SEM) was modified with a large chamber to allow probing wafers. Problems associated with this are getting the test signals onto and off the IC without losses or distortions because of long wire lengths. In (2) another SEM was modified to allow short wire lengths to bring signals to and from the integrated circuit. The modifications to the SEM to accomplish this are substantial and required inverting the column and designing a new chamber/stage assembly.