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Linear Algorithm for Fault Equivalence Groups

IP.com Disclosure Number: IPCOM000056433D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Bloomer, PL Horstmann, PW [+details]

Abstract

The costs of test pattern generation and simulation for logic circuits are increasing as the density of LSI and VLSI (very large-scale integration) chips increases. The computer run times for test generation and simulation can be significantly reduced through the use of fault equivalence groups. This reduction in run time results from the reduction in the size of the fault set used for test generation and simulation. A technique is presented for the efficient determination of fault equivalence groups. A group of faults is said to be equivalent if any test for any fault in the group will detect all of the faults in the equivalence group.