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Generation of Mask Layout from Topological Equations Disclosure Number: IPCOM000056434D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14

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Vergnieres, B [+details]


Manufacturing integrated circuits involves the generation of mask layout. The basic parameters of the design consists of rules as defined by the process technology as well as by the sizes of elements previously determined according to well known simulation techniques.