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An FET (field-effect transistor) conducts in a number of parallel vertical channels that are formed between gate electrodes arranged in parallel fingers for high current capacity.
English (United States)
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Power FET and Manufacturing Method
An FET (field-effect transistor) conducts in a number of parallel vertical
channels that are formed between gate electrodes arranged in parallel fingers for
high current capacity.
In the FET of Fig. 4, conduction takes place in a channel 2 of an N- substrate
3 between a source electrode 4 and a drain electrode 5. N+ regions 6, prevent
the formation of rectifying junctions at the interface of the electrodes and the
substrate. A gate electrode 8 is formed of polysilicon (which is conductive). The
gate is insulated from the substrate and from the source electrode by regions of
silicon dioxide 9, 10, 11 and regions of silicon nitride 12.
Figs. 1, 2 and 3 illustrate a sequence of manufacturing steps. In the steps
preceding Fig. 1, regions 7, 3, and 11', 12' (which become 11, 12 in Fig. 4) and a
layer of silicon dioxide 14 are formed as a sequence of layers. Then, layers 14,
12', 11' and 3 are etched to the shape shown in Fig. 1. Next, the silicon dioxide
layer 9 is formed, and polysilicon is formed in the grooves of gate 8 and over the
entire structure. The polysilicon is then etched to the configuration of Fig. 1.
In the steps leading to Fig. 2, regions 14 are removed by using hydrofluoric
acid, and a layer of silicon dioxide 10' is formed (which in part becomes 10 in Fig. 4).
In the steps leading to Fig. 3, silicon dioxide layer 10' is etched to expose the
silicon nitride layer 12 for a subsequent step of forming the source electro...