Memory with Selective use of Error Detection and Correction Circuits
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14
Memory cycle time is reduced by eliminating error detection and correction operations when a fetch is made to a storage location where there has been a recent store operation. Store addresses are loaded into a push-down register, and the contents of the register identify storage locations where an error is sufficiently unlikely that the error detection and correction operation can be skipped.