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Charge Coupled Device on N-Wafer

IP.com Disclosure Number: IPCOM000056465D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Anolick, ES Chen, LY Ko, SB [+details]

Abstract

Above 3 MeV energy, for normal incidence of alpha particles, there is a leveling off of bit errors. This is attributed to the recombination and/or sharing of minority carriers (which are generated deep in the p-wafer) by the various cells. If the carriers generated closer to the surface can be swept away from the cell regions, then the number of bit errors generated can be reduced.