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Technique for Extended Addressability

IP.com Disclosure Number: IPCOM000056477D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Kusmiss, JM [+details]

Abstract

In a processor with 128K of real storage and using address range control, two bits of a processor status word (PSW) may control the access range in main storage (MS) to which the current instruction operand addresses are accessed in a MS greater than the size of the program addressability. These two bits may be set to 0 and other PSW bits may indicate no address relocation. With a base of 0, it is only possible to access storage operands in 0 - 64KB absolute address range in main storage. If a base of 64K is used to relocate storage operand absolute addresses to 64 128K, then simultaneous access to instruction addresses in the absolute 0 - 64KB range are not possible, since instruction addresses are relocated.