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System Cache for High Performance Processors

IP.com Disclosure Number: IPCOM000056478D
Original Publication Date: 1980-Dec-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Desai, SM [+details]

Abstract

Most of the current high performance processors have a small high-speed buffer (cache) in front of a large relatively slow main memory, to reduce the average access time. There are mainly two methods used to manipulate the data between the cache and the main memory. One is the "Store-in-Buffer", and the other is the "Store-Thru-Buffer". Both schemes have their advantages and limitations. With improved technology allowing smaller and smaller machine cycle time, the limitations cause considerable performance loss. The loss increases in multiprocessing designs. The design described below combines the advantages of both the above methods by introducing another level of buffering called "System Cache".