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Vertical Partitioning in Cache Hierarchies

IP.com Disclosure Number: IPCOM000056586D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Liu, L [+details]

Abstract

A technique is described whereby a computer cache memory is partitioned into vertical hierarchies, so as to avoid duplication of cache lines in two level hierarchies. It is an improvement over previous hierarchies, since the efficiency of the cache circuits is improved. In two-level cache hierarchies, (L1/L2), the first level cache is typically maintained more or less as a subset of the second level. For example, with reasonable sizing, when L2 is twice as big of L1, maintaining disjointedness of L1/L2 will provide close to 40% better miss ratio to the hierarchy. Therefore, the concept described herein provides a method for maintaining L1 and L2, such that the caches are disjoint.