Operand Buffer Hit Prediction Mechanism
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14
A pipeline computer has an operand buffer and a cache memory. An operand prediction system determines during the address generation cycle if the operand is in the buffer. If a buffer hit occurs, the cache is not accessed. If a buffer miss occurs, the cache is accessed in a conventional manner. This disclosure applies to a machine design having the capability of fetching operands to an operand buffer and having the ability to subsequently re-access that data as though it were part of storage. The mechanism described herein has the effect of decreasing fetch request traffic to the cache by predicting the presence of data in the operand buffer.