Address Transition Detection Enhancement Circuit
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14
An address transition detect circuit provides a stable and reliable control pulse for a static random-access memory under adverse input signal-to-noise conditions. Address transition detection (ATD) of an input pulse is critical in the timing of asynchronous static random-access memories (SRAMs) because it initiates a memory cycle and is also used to determine the length of a chip restore period. Pulses from the address receiver are timed to be long enough for proper chip restore but can lose pulse integrity when an input signal glitches just prior to an actual pulse transition. This could be due to an interrupt or other asynchronous event. The disclosed circuit eliminates glitch sensitivities by allowing the transition detection pulse to be narrow and therefore responsive to changes at the input.