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Architecture for a High-Speed Memory Tester

IP.com Disclosure Number: IPCOM000056606D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Blackwell, JC Bogholtz, R Bosch, L Gallagher, DM Mezzacappa, VJ Mitchell, TH Ostlie, LE Smith, RK [+details]

Abstract

Available high-speed memory testers have been found incompatible with certain requirements imposed upon them, for example, the need for the simultaneous test of two levels of memory, as would be the case shown in Fig. 1. The general characteristics of multi-level memories that contribute to this problem are: 1) A relative speed difference between memory cycles of an order of magnitude, with the faster memory cycle being at the leading edge of the technology, and 2) An unrestricted overlap of the read and write cycle for the faster memories and some restricted overlap with the slower ones.