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Test Apparatus for Buffered Array Chip

IP.com Disclosure Number: IPCOM000056612D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Aichelmann, FJ [+details]

Abstract

By adding additional circuits to the buffer contained in array chips in semiconductor devices, the testing of the chips is facilitated since it permits comparison of the data in the data register with the data entered in the data gate register. Buffers are incorporated in high performance memory applications to sustain the data rate from the selected chip. Larger buffers are required as performance demands increase since the chip's continuous transfer rate cannot fill the buffer fast enough for the applications. A memory array chip (Fig. 1) includes an on-chip buffer between the array and the I/O interface. The functional block diagram of Fig. 2 shows a buffered array chip with its corresponding data register and associated data gate register.