Multiplexed Address Detection Method
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14
The present scheme modifies part of the written data when writing to address lines of semiconductor devices so as to improve the checking of the data's redundancy. The technique requires one less address line than does other approaches to the operation. Multiplexed addresses utilized in memory applications usually originate from supports on an array card. If an address line becomes stuck, but drives a set of redundantly-coded data, such as error checking and correction (ECC) or parity, the stuck address line is undetectable. This condition occurs since the stuck address line causes the correct data to be stored in the wrong location and to be read from the wrong location. The new scheme biases the ECC word based upon an address partition and designation. Two forms of ECC biasing are indicated in Fig. 1.