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Glitch/Noise-Free Dynamic RAM Address Multiplexing for Multiple Address Inputs

IP.com Disclosure Number: IPCOM000056653D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Thompson, SP [+details]

Abstract

This article describes a circuit arrangement which isolates dynamic RAMs (DRAMs) from glitches introduced by address switching and from noise introduced by external address sources. (Image Omitted) In DRAM applications with multiple address sources (e.g., video applications), glitch/noise-free address selection and row address selection-column address selection (RAS-CAS) address multiplexing can be done by using a two-level multiplexer scheme. The scheme uses separate RAS address and CAS address multiplexers feeding a single RAS/CAS multiplexer as shown in the block diagram of Fig. 1. The RAS address multiplexer selects which address source the DRAM RAS address will come from. Similarly the CAS address multiplexer selects which address source the DRAM CAS address will come from.