Browse Prior Art Database

Circuit to Generate Input/Output Read, Write and Ready Signals for Computer Bus Compatibility

IP.com Disclosure Number: IPCOM000056655D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Lin, HC Vyas, RM [+details]

Abstract

A technique is described whereby a circuit generates input/output (I/O) read, write and channel ready signals so as to provide compatibility to computers which have high-speed interface bus requirements, enabling them to function with peripheral devices which operate at various speeds. The circuit is unique in that it not only provides the high- speed functional operational bus interface compatibility for faster computers but enables slower speed computers to also function with various peripherals through the use of wait states built into the circuitry. The circuit, as shown in the figure on the preceding page, is designed for use with asynchronous communication element, such as National Semiconductor's NS16550 or equivalent, which have special interface timing requirements.