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Indexing Facility for Processors Disclosure Number: IPCOM000056663D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

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Brady, JT [+details]


A new system architecture is described for facilitating the addressing of data arrays. The new architecture has at least three index register sets and each index register set has a multiplicity of dimensions. By way of example, consider one such architecture which has three index registers (A,B,C) each of which has four dimensions (1,2,3,4). Let: SPAN (S) - the number of bits in an array element specified as a power of 2. INCREMENT - a signed number which specified the number of SPANs that a dimension is to be incremented by the Increment Index and Branch, the Increment Index and Conditionally Branch, and the Branch and Increment Index Registers instructions (infra). INDEX (I) - the active value for a dimension of an index register.