Browse Prior Art Database

Twice Redundant Radiation Hardened Latch

IP.com Disclosure Number: IPCOM000056664D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Hoffman, JA [+details]

Abstract

Traditional methods of hardening static latches and memory elements against ionizing radiation rely on resistive hardening (via time discrimination), oversized devices, or capacitive hardening. Resistive hardening results in a long slow access time, while oversize devices and capacitive techniques have a large area penalty. The disclosed circuit requires only a moderate area increase over non-hardened mechanisms, and has a fast write access time. The circuit disclosed uses two redundant storage elements composed of transistors T5-T12 and T14-T15. Data is written into the latches via three parallel paths, T13-T15, allowing a fast write access. The output data present on nodes B1-B3 is algebraically summed at node C, and buffered by T16-T17.