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Integration of Performance Tuning Into Incremental VLSI Chip Design

IP.com Disclosure Number: IPCOM000056665D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Masleid, RP Patel, PT Stephenson, M [+details]

Abstract

A method is described for computing performance which can operate on any mixture of design development within a VLSI design. The method achieves this through a flexible Manhattan distance type algorithm and capacitance stored hierarchically on pins. The method also provides ability to integrate performance tuning with physical design cycle which minimizes the overall design cycle. Existing VLSI performance tuning tools have two major problems. First, they require that all sections of the design have reached some common level of development, such as placement, wiring, etc. Second, none accept floorplanning information wherein a particular block's location has been refined only to a region, if at all. The result is that performance data lags well behind the state of design.