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Building Block Multiprocessor Architecture

IP.com Disclosure Number: IPCOM000056671D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Kukula, JH [+details]

Abstract

Various data-processing systems have been proposed and built which are based on a set of interconnected general-purpose computers. Expandability of such systems is a desirable feature. The problem which needs to be solved in order to achieve expandability is maintaining communication channels between many processors. If all processors communicate via a common bus, then for some number of processors the bus will reach its capacity, and a limit of expansion has been reached. Thus, an effective expansion technique must include many busses, and a limited number of processors on each bus. In the described architecture, the body of the machine is built of repetitions of a single building block 10, shown in Fig. 1. Each building block contains two processing elements 11 and 12 and three busses A-C.