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Process Techniques for Merging Bipolar and CMOS Devices on the Same Chip

IP.com Disclosure Number: IPCOM000056685D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Bracchitta, J El-Kareh, B [+details]

Abstract

CMOS process techniques that allow a merger of bipolar and field-effect transistor (FET) devices on the same chip is outlined. By making multiple use of existing process steps and masks in order to reduce overall process complexity, high density/high performance static random-access memories (SRAMs) and high performance bipolar devices can be fabricated on the same chip while allowing the designer to make trade-offs between optimizing bipolar or FET characteristics, depending upon the application. The figure shows FET devices (NMOS and PMOS), bipolar devices (NPN and PNP) and a Schottky barrier diode on the same chip.