Browse Prior Art Database

Pass Gate Multiplexer Testing by Direct Current Measurement

IP.com Disclosure Number: IPCOM000056689D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Ogilvie, CR [+details]

Abstract

Multiplexers are tested by adding one additional transistor for each multiplexer on a chip. Test procedures are described to identify chips having failures in any multiplexer or in the added test circuits. Referring to the diagram, transistors T2, T4 and T6 are added, as shown, to multiplexer circuits M2, M4 and M6, respectively. Gates of transistors T2, T4, T6 are tied together and attached to primary input pad N2. Data inputs of transistors T2, T4 and T6 are tied together and brought out to pad N4. In order to test all multiplexers, output nodes of all multiplexers are placed in a high impedance state, i.e., all gates of multiplexer devices are turned off (set at zero volts). The following two tests are performed to determine whether any short circuit conditions exist in any of the multiplexers, M2, M4 or M6.