Browse Prior Art Database

Fast Handling of Load Upper and Convert Binary Instruction to Enhance Binary Floating-Point Performance

IP.com Disclosure Number: IPCOM000056690D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Goldberg, WD Olsson, B Suarez, GA [+details]

Abstract

This article describes a technique which reduces multicycle load upper and convert binary (LUCB) instruction time to one effective machine cycle. The IEEE Binary FP Standard 754-1985 defines a binary floating- point (FP) arithmetic. The standard supports conversions between the different data formats (single-precision, double-precision, double extended, and short and long integer). An architecture supporting the standard FP instructions is issued as processor bus operations (PBOs), including those which load/copy data between the CPU's general-purpose registers (GPRs) and the floating-point registers (FPRs). A high performance FP unit, adhering to the above standard, can be designed which allows for maximum execution overlap of the PBOs.