Apparatus for Detection and Isolation of Failures
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14
A method is disclosed for detecting and isolating failures in a bus interface between the processor and memory or other computer elements. This approach compares the signal on the bus with a signal generated by the sending device ahead of the bus driver. The XOR circuit takes as the input the signal to and from the input and output of the bus driver, respectively. The output of the XOR circuit feeds a common OR circuit with other bus elements. A timed latch is used to trap any errors. (Image Omitted) Where products or chips are dotted on a bus, a failure within the interface can lead to errors. While error checking and correction (ECC) logic can provide detection and correction to the system, the field replaceable unit (FRU) isolation and percent detectability may not be of a sufficiently high order.