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Gapless Planarized Structures for Integrated Electronic Packaging Disclosure Number: IPCOM000056702D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

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Brady, MJ Shaw, JM Yee, DS [+details]


A technique is described whereby a process produces planarized circuit structures without the inclusion of gaps or voids in the circuit medium, as used in the fabrication of semiconductor integrated circuitry. The process can be applied to many applications employing the use of metal or non-metal lines. Typical applications are in low level multi-level integrated circuit structures. In prior art, fabrication of planar circuit structures involved precise control of process parameters and required complicated equipment and procedures. Line-of-sight deposition, such as evaporation, magnetron-sputtered deposition, as well as ion beam-assisted evaporation, have been used to produce the structures. The technique described herein utilizes a photoimagable polyimide in the fabrication process.