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Priority Controller for Bus Arbiter Disclosure Number: IPCOM000056712D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

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Ohba, N [+details]


This article describes a new priority control mechanism for bus arbiters and a new hardware circuit that realizes the high-speed priority control based on it. Bus arbiters are used to arbitrate bus requests which are simultaneously offered by more than two bus masters. When the bus arbiter detects bus requests, it selects only one bus master and returns the bus grant to it. In order for efficient resource utilization, it is desired to give fair priorities to all bus masters. This disclosure provides a new rotating priority scheme that realizes the fair priority control. The features of this disclosure are: 1.Rotating priority scheme for a fair bus priority. 2.High-speed arbitration by two matrix blocks. Fig.