Browse Prior Art Database

Transparent Update Memory System

IP.com Disclosure Number: IPCOM000056724D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Bonnet, R Borgis, PH Gallezot, R [+details]

Abstract

The contents of a memory device attached to a processor is conventionally being repetitively refreshed through read/modify/write operations performed sequentially at a high rate, say, of 120 nanoseconds. After the read cycle, the memory contents is modified if needed and reloaded during the write cycle. When the highest memory address is reached, address counters are reset and a new memory scanning cycle is started. Consequently, any processor transfer from or to the memory needs to be synchronized with the sequential memory refresh operation. Obviously, this mechanism does not optimize the processor operation, since the locations to be accessed by the processor are anywhere in the memory and not necessarily consecutive.