TTL Level High Speed BIFET Receiver
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14
The BIFET process which mixes a CMOS and Bipolar transistor on the same chip can be used for the design of a receiver circuit with a better power performance factor of merit than the bipolar or the CMOS taken alone. As shown in the drawing, the proposed BIFET receiver is based on a bipolar differential amplifier as input. It converts TTL levels (0.6 V max down level, 2.4 V min Up level) to CMOS levels (0,5 V) for CMOS logic or RAM circuits. This receiver is designed without Schottky barrier diodes (SBDs), but it achieves the same speed as the receiver built with SBDs for antisaturation. The input of the circuit is done on the base of T1 of the differential circuit T1, T2, with the base of T2 connected to a 1.5 V reference threshold of TTL circuits. The amplified signal across R1 is then shifted from one VBE = 0.