Clock Splitter in Cmos Gate Array
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14
This article describes a circuit which generates two non-overlapping clocks. As shown in Fig. 1, the proposed circuit consists of one inverter, two NANDs and two delay blocks. The drive capability is achieved using two output buffers. This logical representation is implemented as shown in Fig. 2, and the circuit operation is described by the timing diagram in Fig. 3. When the A0 clock goes up, the falling transition on the "out of phase" output (20) takes place first and after the "in phase" output (10 goes up and becomes active. When the A0 clock goes down, the output 10 becomes inactive first, and the output 20 becomes active afterwards.