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Bus Control Block List Concept and Management Mechanism

IP.com Disclosure Number: IPCOM000056744D
Original Publication Date: 1988-Jan-01
Included in the Prior Art Database: 2005-Feb-14

Publishing Venue

IBM

Related People

Authors:
Duffield, NJ Marquart, DW Morse, RD [+details]

Abstract

A channel or data transfer bus system in connection with a computer that allows transmission of messages and transfer of data in packets requires a good deal of control to keep messages flowing and data packets moving. This may be accomplished by direct software control of the data bus interface hardware, at the expense of many interactions and (possibly expensive) interruptions from the hardware. This mechanism constitutes a way for hardware to handle much of the detail work of managing such a bus. The interface hardware contains a set of registers that control data transfer. One is the address of a Bus Control Block (BCB); others are control registers that allow the processor to start and stop data transfers, and to read the status of data transfers. The BCB is defined below.